The need to remain competitive in cost and performance in the production of semiconductor devices elevates demand to continually increase the device density of integrated circuits. To achieve higher degrees of integration with the miniaturization in semiconductor integrated circuitry, robust methodologies are required to reduce the scale of the circuit pattern formed on the semiconductor substrate. These trends and requirements impose ever-increasing challenges on the ability to prepare electrical structure isolation during circuit pattern fabrication.
Photolithography is a mainstay technique used to manufacture semiconductor integrated circuitry by transferring geometric shapes and patterns on a mask to the surface of a semiconductor wafer. In principle, a light sensitive material is exposed to patterned light to alter its solubility in a developing solution. Once imaged and developed, the portion of the light sensitive material that is soluble in the developing chemistry is removed, and the circuit pattern remains. Furthermore, to advance optical lithography, as well as accommodate the deficiencies thereof, continual strides are being made to establish alternative patterning strategies to equip the semiconductor manufacturing industry for sub-30 nm technology nodes.
In concert with advanced patterning techniques, advanced, highly selective etching techniques are required to transfer sub-30 nm features. Additionally, advanced etching schemes are challenged to meet requirements for profile control, anisotropy, and rate, among other things.